The present invention relates generally to systems and methods for processing video data. More specifically, the present invention relates to efficient systems and methods for performing motion compensation based decoding and recoding.
Video data is transmitted in a bitstream, or a continuous sequence of binary bits used to digitally represent compressed video, audio or data. The bitstream is transmitted over a transmission channel. One problem with existing transmission channels is their ability to transport video data. In multimedia streaming applications for example, the video data requires significant bandwidth from a communication channel. Since transmission of video data with existing communication channels is often excessive, compression is an approach that has been used to make digital video images more transportable. Digital video compression schemes allow digitized video frames to be represented digitally in much more efficient manner. Compression of digital video makes it practical to transmit the compressed signal using digital channels at a fraction of the bandwidth required to transmit the original signal before compression.
International standards have been created for video compression schemes. These include MPEG-1, MPEG-2, MPEG-4, H.261, H.262, H.263, H.263+, etc. These standardized compression schemes rely on several algorithm schemes such as motion compensation, transform coding (for example, DCT transforms or wavelet/sub-band transforms), quantization of the transform coefficients, and variable length coding (VLC).
Motion compensation removes the temporally redundant information between video frame sequences. Motion compensation of an MPEG compressed bitstream includes an iterative process where I, P and B frames are reconstructed using a reference framestore memory, or frame buffer. The framestore memory contains reconstructed image samples from the input compressed bitstream. In most cases, on-chip memory is insufficient to hold the video data for an entire reference frame. With an HDTV signal for example, the framestore memory may need up to 12 MB of memory if an entire frame is used for motion compensation. Thus, the framestore memory or frame buffer is typically an off-chip memory source. Using off-chip memory may dramatically slow down motion compensation of compressed video.
More specifically, motion compensation for a block is a three-step process. The first step is to retrieve a reference block of pixel values from the reference framestore memory and to retrieve a block of pixel values just decoded from a decoded framestore memory. The second step is to perform motion compensation, which includes a summation of all pixel values for the block. The last step is to move the summed block back to the decoded framestore memory. This three-step process is performed in sequence for each block in a macroblock before selecting and processing the next macroblock in a frame.
The sequential and repetitive nature of block transfers from the framestore memories produces significant delay. Video typically includes more than a thousand of frames per minute, and more than a thousand blocks per frame. This delay may compromise timely transmission and decoding of video data. For example, transmission of video data is often intended for real-time playback. This implies that all of the information required to represent a digital picture must be delivered and displayed in a timely manner. Thus, motion compensation applied during decoding or recoding must be performed quickly. In a digital video broadcast where thousands of bitstreams are transmitted for example, undesirable processing delays may compromise broadcast transmission.
Therefore, there is a need for efficient methods and systems of performing motion compensation without incurring undesirable delays.